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MC14503B Hex Non-Inverting 3-State Buffer
The MC14503B is a hex non-inverting buffer with 3-state outputs, and a high current source and sink capability. The 3-state outputs make it useful in common bussing applications. Two disable controls are provided. A high level on the Disable A input causes the outputs of buffers 1 through 4 to go into a high impedance state and a high level on the Disable B input causes the outputs of buffers 5 and 6 to go into a high impedance state.
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16 MC14503BCP AWLYYWWG 1
* 3-State Outputs * TTL Compatible -- Will Drive One TTL Load Over Full * * * *
Temperature Range Supply Voltage Range = 3.0 Vdc to 18 Vdc Two Disable Controls for Added Versatility Pin for Pin Replacement for MM80C97 and 340097 Pb-Free Packages are Available*
1
PDIP-16 P SUFFIX CASE 648
SOIC-16 D SUFFIX CASE 751B 1
16 14503BG AWLYWW 1
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1)
Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input Current (DC or Transient) per Pin Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Symbol VDD Vin, Vout Iin Iout PD TA Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 25 500 -55 to +125 -65 to +150 260 Unit V V mA mA mW C C C 1 SOEIAJ-16 F SUFFIX CASE 966
16 MC14503B ALYWG 1
A WL, L YY, Y WW, W G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
June, 2006 - Rev. 7
Publication Order Number: MC14503B/D
MC14503B
PIN ASSIGNMENT
DIS A IN 1 OUT 1 IN 2 OUT 2 IN 3 OUT 3 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD DIS B IN 6 OUT 6 IN 5 OUT 5 IN 4 OUT 4 Inn 0 1 X X = Don't Care
TRUTH TABLE
Appropriate Disable Input 0 0 1
Outn 0 1 High Impedance
LOGIC DIAGRAM
DISABLE B IN 5 IN 6 IN 1 IN 2 IN 3 IN 4 DISABLE A 15 12 14 2 4 6 10 1 VDD = PIN 16 VSS = PIN 8 11 13 3 5 7 9 OUT 5 OUT 6 OUT 1 OUT 2 OUT 3 OUT 4 *DISABLE * INPUT TO OTHER BUFFERS *IN n
CIRCUIT DIAGRAM
ONE OF TWO/FOUR BUFFERS VDD
OUTn
VSS
*Diode protection on all inputs (not shown)
ORDERING INFORMATION
Device MC14503BCP MC14503BCPG MC14503BD MC14503BDG MC14503BDR2 MC14503BDR2G MC14503BFEL MC14503BFELG Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOEIAJ-16 SOEIAJ-16 (Pb-Free) 2000 / Tape & Reel 2500 / Tape & Reel 48 / Rail 25 / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III III III III II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III II I I I I I I I I I I III III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III III III III IIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III II III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I I III III III III I IIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
3. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 4. The formulas given are for the typical characteristics only at 25_C. 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.006.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
3-State Output Leakage Current
Total Supply Current (Note 4, 5) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs) (All outputs switching, 50% Duty Cycle)
Quiescent Current, (Per Package)
Input Capacitance, (Vin = 0)
Input Current
Output Drive Current (VOH = 2.5 Vdc) (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc)
Input Voltage (VO = 3.6 or 1.4 Vdc) (VO = 7.2 or 2.8 Vdc) (VO = 11.5 or 3.5 Vdc)
Output Voltage Vin = 0
(VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)
(VO = 1.4 or 3.6 Vdc) (VO = 2.8 or 7.2 Vdc) (VO = 3.5 or 11.5 Vdc)
Vin = VDD
Characteristic
"0" Level
"0" Level
"1" Level
"1" Level
Source
Sink
Symbol
VOH
VOL
IOH
VIH
Cin
IOL
VIL
ITL
IQ
Iin
IT
VDD
Vdc
5.0 10 15
5.0 10 15
4.5 5.0 10 15
4.5 5.0 5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
15
-
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MC14503B
4.95 9.95 14.95
- 4.3 - 5.8 - 1.2 - 3.1 - 8.2
2.2 2.6 6.5 19.2
Min
3.5 7.0 11
-
- - -
-
-
- - -
- - -
- 55_C
3 0.1 0.1 0.05 0.05 0.05 Max 1.0 2.0 4.0 1.5 3.0 4.0 - - - - - - - - - - - - - - - - - 3.6 - 4.8 - 1.02 - 2.6 - 6.8 4.95 9.95 14.95 1.8 2.1 5.5 16.1 Min 3.5 7.0 11 IT = (2.5 mA/kHz) f + IDD IT = (6.0 mA/kHz) f + IDD IT = (10 mA/kHz) f + IDD - - - - - - - - - - - - 0.00001 0.0001 Typ (Note 3) - 5.0 - 6.1 - 1.4 - 3.7 - 14.1 0.002 0.004 0.006 25_C 2.75 5.50 8.25 2.25 4.50 6.75 5.0 2.1 2.3 6.2 25 5.0 10 15 0 0 0 0.1 0.1 0.05 0.05 0.05 Max 1.0 2.0 4.0 7.5 1.5 3.0 4.0 - - - - - - - - - - - - - - - 4.95 9.95 14.95 - 2.5 - 3.0 - 0.7 - 1.8 - 4.8 1.2 1.3 3.8 11.2 Min 3.5 7.0 11 - - - - - - - - - - - - 125_C 3.0 1.0 0.05 0.05 0.05 Max 30 60 120 1.5 3.0 4.0 - - - - - - - - - - - - - - - - mAdc mAdc mAdc mAdc mAdc mAdc Unit Vdc Vdc Vdc Vdc pF
MC14503B
SWITCHING CHARACTERISTICS (Note 6) (CL = 50 pF, TA = 25_C)
III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II II I I IIIIIIIIIIIIII II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II II I I IIIIIIIIIIIIII II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II II I I IIIIIIIIIIIIII II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II II I I III I I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II II I I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II II I I III I I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II II I IIIIIIIIIIIIII II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I III I I I II I I I IIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I I I IIIIIIIIIIIIIIIIII
All Types Characteristic Symbol tTLH VDD VCC 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Typ (Note 7) 45 23 18 45 23 18 75 35 25 75 35 25 75 40 35 80 40 35 65 25 20 Max 90 45 35 90 45 35 Unit ns Output Rise Time tTLH = (0.5 ns/pF) CL + 20 ns tTLH = (0.3 ns/pF) CL + 8.0 ns tTLH = (0.2 ns/pF) CL + 8.0 ns Output Fall Time tTHL = (0.5 ns/pF) CL + 20 ns tTHL = (0.3 ns/pF) CL + 8.0 ns tTHL = (0.2 ns/pF) CL + 8.0 ns tTHL ns Turn-Off Delay Time, all Outputs tPLH = (0.3 ns/pF) CL + 60 ns tPLH = (0.15 ns/pF) CL + 27 ns tPLH = (0.1 ns/pF) CL + 20 ns Turn-On Delay Time, all Outputs tPHL = (0.3 ns/pF) CL + 60 ns tPHL = (0.15 ns/pF) CL + 27 ns tPHL = (0.1 ns/pF) CL + 20 ns 3-State Propagation Delay Time Output "1" to High Impedance Output "0" to High Impedance tPLH ns 150 70 50 150 70 50 150 80 70 160 80 70 130 50 40 200 70 50 tPHL ns tPHZ ns tPLZ ns High Impedance to "1" Level tPZH ns High Impedance to "0" Level tPZL 100 35 25 ns 6. The formulas given are for the typical characteristics only at 25_C. 7. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. DISABLE INPUT 20 ns VDD 16 INPUT OUTPUT VSS CL INPUT tPLH OUTPUT 90% tTLH tPLH 50% 90% 50% 20 ns VDD 10% tPHL 10% VSS VOH PULSE GENERATOR VOL tTHL tPHL
Figure 1. Switching Time Test Circuit and Waveforms (tTLH, tTHL, tPHL, and tPLH)
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MC14503B
PULSE GENERATOR DISABLE INPUT VDD 16 OUTPUT 8 VSS 1k CL INPUT 8 VSS CL PULSE GENERATOR 16 DISABLE INPUT VDD 1k OUTPUT tPLZ, tPZL CIRCUIT
tPHZ, tPZH CIRCUIT INPUT
20 ns 50% DISABLE INPUT tPLZ 10% tPHZ OUTPUT FOR tPHZ, tPLZ CIRCUIT 90% 10% 90%
20 ns 10% tPZL 90%
VDD VSS VOH
OUTPUT FOR tPZH, tPZL CIRCUIT
VOL + 0.05 V tPZH VOH - 0.15 V VOL
Figure 2. 3-State AC Test Circuit and Waveforms (tPLZ, tPHZ, tPZH, tPZL)
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MC14503B
PACKAGE DIMENSIONS
PDIP-16 CASE 648-08 ISSUE T
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16 CASE 751B-05 ISSUE J
-A-
16 9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC14503B
PACKAGE DIMENSIONS
SOEIAJ-16 CASE 966-01 ISSUE A
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC14503B/D

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